Debjit Pal

Debjit Pal

Post-Doctoral Associate

Cornell University


I am a Post-Doctoral associate in the School of Electrical and Computer Engineering at Cornell University and a member of the Computer Systems Laboratory. My research concerns new algorithms, methodologies, and design automation tools for building correct and dependable computing systems via synergistic applications of specification, architecture, and validation technologies. Specifically, my recent publications focus on post-silicon and pre-silicon validation of System-on-Chips (SoCs), application of machine learning for high-level synthesis and hardware resiliency, and security validation. My research has been recognized with IEEE CEDA Student Research Award (2016) and three best paper nominations (ICCAD'15, DAC'18, ASP-DAC'19).

Prior to joining Cornell, I received my Ph.D. in Computer Engineering from the University of Illinois at Urbana-Champaign (UIUC). I have a B.E in Electronics Engineering from Jadavpur University and an M.S. in Computer Science from IIT Kharagpur.

Research Interests

  • Machine Learning for Electronic Design Automation (EDA)
  • Reconfigurable Computing, Compiler Optimizations for High-Performance Computing
  • System-on-Chip (SoC) Verification
  • Edge Intelligence (EI) as Service, Trustworthy EI


Professional Services

  • Technical Program Committee (TPC) Member
    • Design Automation Conference (DAC) (2021, 2020)
    • VLSI Design Conference (VLSID) (2021, 2020)
  • Reviewer
    • Journal: IEEE TVLSI (2019, 2018, 2017), IEEE TCAD (2020, 2016), IEEE TC (2019), ACM TODAES (2019)
    • Conference: DAC (2019, 2018, 2017, 2016, 2015, 2014), DATE (2021, 2019, 2018, 2017), ICCAD (2018, 2017), FMCAD (2016), IWLS (2020), FPGA (2021), ASPLOS-LATTE Workshop (2021)


Quickly discover relevant content by filtering publications.
(2021). GLAIVE: Graph Learning Assisted Instruction Vulnerability Estimation. IEEE Design Automation and Test in Europe.


(2020). Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks. IEEE/ACM International Conference On Computer Aided Design (ICCAD).


(2020). Assertion Ranking Using RTL Source Code Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (TCAD).


(2020). Emphasizing Functional Relevance Over State Restoration in Post-Silicon Signal Tracing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst (TCAD).



1 of the 7 semi-finalists in E. J. McCluskey Best Doctoral Thesis competiton
Best Paper Nomination (11 out of 304 submmissions)
Travel grant for Student Research Competition at ICCAD
1 of the 15 semi-finalists in Student Research Competiton
Fall 2018 travel grant for ASP-DAC 2019
Ph.D. Forum
Ph.D. Forum
Best Paper Nomination (8 out of 691 submmissions)
Travel grasnt for Ph.D. forum
IEEE CEDA SVDTC Student Research Award 2016
Best Paper Nomination (4 out of 382 submmissions)
Bronze Medal for Second Highest Aggregate of Marks in Bachelor of Engineering
Fellowship for International Conference on VLSI Design